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| www.fairchildsemi.com KA3524 SMPS Controller Features Complete PWM power control circuit Operation beyond 100KHz 2% frequency stability with temperature Total quiescent current less than 10mA Single ended or push-pull outputs Current limit amplifier provides external component protection * On-chip protection against excessive junction temperature and output current * 5V, 50mA linear regulator output available to user * * * * * * Description The KA3524 regulating pulse width modulator contains all of the control circuit necessary to implement switching regulators of either polarity, transformer coupled DC to DC converters, transformerless polarity converters and voltage doublers, as well as other power control applications. This device includes a 5V voltage regulator capable of supplying up to 50mA to external circuit , a control amplifier, an oscillator, a pulse width modulator, a phase splitting flip-flop, dual alternating output switch transistors, and current limiting and shut-down circuit. Both the regulator output transistor and each output switch are internally current limiting and, to limit junction temperature, aninternal thermal shutdown circuit is employed. 16-DIP 1 Internal Block Diagram Rev. 5.0 (c)2000 Fairchild Semiconductor International KA3524 Absolute Maximum Ratings Parameter Supply Voltage Reference Output Current Output Current (Each Output) Oscillator Charging Current (pin 6 or 7) Lead Temperature (Soldering, 10 sec) Power Dissipation (TA = 25C) Operating Temperature Storage Temperature Symbol VCC IREF IO ICHG(OSC) TLEAD PD TPOR TSTG Value 40 50 100 5 300 1000 0 ~ +70 -65 ~ + 150 Unit V mA mA mA C mW C C Electrical Characteristics (VIN=20V, f=20KHz, TA = 0 to +70C, unless otherwise specified) Parameter REFERENCE SECTION Reference Output Voltage Line Regulation Load Regulation Ripple Rejection Short-Circuit Output Current Temperature Stability Long Term Stability OSCILLATOR SECTION Maximum Frequency Initial Accuracy Frequency Change with Voltage Frequency Change with Temperature Clock Amplitude (Pin 3) Clock Width (Pin 3) ERROR AMPLIFIER SECTION Input Offset Voltage Input Bias Current Open Loop Voltage Gain Common-Mode Input Voltage Common-Mode Rejection Ratio Small Signal Bandwidth Output Voltage Swing VIO IBIAS GVO VCM CMRR BWSS VO(ERR) TA = 25C TA = 25C GV = 0dB, TA= 25C TA = 25C VCM = 2.5V VCM = 2.5V 60 1.8 0.5 2 2 80 70 3 10 10 3.4 3.8 mV A dB V dB MHz V f(MAX) ACCUR f/VCC f/T V(CLK) tW(CLK) CT = 0.001uF, RT = 2K RT and CT constant VCC = 8V to 40V, TA = 25C Over operating temperature range TA = 25C CT = 0.01uF, TA = 25C 350 5 3.5 0.5 1 2 KHz % % % V s VREF VREF VREF RR ISC STT ST TA = 25C VCC = 8V to 40V IREF = 0 mA to 20 mA f = 120Hz, TA = 25C VREF = 0, TA = 25C 4.6 5.0 10 20 66 100 0.3 20 5.4 30 50 1 V mV mV dB mA % mV/KHr Symbol Conditions Min. Typ. Max. Unit 2 KA3524 Electrical Characteristics (VIN=20V, f=20KHz, TA=0C to +70C, unless otherwise specified) Parameter COMPARATOR SECTION Maximum Duty Cycle Input Threshold (Pin 9) Input Threshold (Pin 9) Input Bias Current CURRENT LIMITING SECTION Sense Voltage VSENSE V2 - V150mV V9 = 2V, TA = 25C VCE = 40V IC = 50mA VC = 20V RC = 2K, TA = 25C RC = 2K, TA = 25C VCC =40V, PINS 1,4,7,8,11 and 14 are grounded, V2=2V All other inputs and Outputs open 180 0.7 40 17 200 0.2 0.1 1 18 0.2 0.1 5 220 1 50 2 10 mV mV/C V V A V V s s mA D(MAX) VTH1 VTH2 IBIAS % Each output on Zero duty cycle Maximum duty cycle 45 1 3.5 1 % V V A Symbol Conditions Min. Typ. Max. Unit Temperature Coefficient of Vsense VSENSE/T Common-Mode Voltage OUTPUT SECTION (EACHOUTPUT) Collector-Emitter Voltage Collector Leakage Current Saturation Voltage Emitter Output Voltage Rise Time (10 to 90) Fall Time (90 to 10) Supply Current VCEO ILKG VCE(SAT) VE tR tF ICC VCM 3 KA3524 Application Information Voltage Reference An internal series regulator provides a nominal 5 volt output which is used both to generate a reference voltage and is the regulated source for all the internal timing and controlling circuitry. This regulator may be bypassed for operation from a fixed 5 volt supply by connecting pins 15 and 16 together to the input voltage. In this configuration, the maximum input voltage is 6.0 volts. This reference regulator may be used as a 5 volt source for other circuitry. It will provide up to 50mA of current itself and can easily be expanded to higher current with an external PNP as shown in Figure 2. Expanded Reference Current Capability Oscillator The oscillator in the KA3524 uses an external resistor (RT) to establish a constant charging current into an external capacitor (CT), While this uses more current than a series connected PC, it provides a linear ramp voltage on the capacitor which is also used as a reference for the comparator. The charging current is equal to 3.6V/RT and should be kept within the range of approximately 30uA to 2mA, i.e., 1.8K< RT <100K. The range of values for CT also has limits as the discharge time of Ct determines the pulse width of the oscillator output pulse. This pulse is used (among other things) as a blanking pulse to both outputs to insure that there is no possibility of having both outputs on simultaneously during transitions. This output dead time relationship is shown in Figures. A pulse width below approximately 0.5 microseconds may allow false triggering of one output by removing he blanking pulse prior to the flip-flops reaching a stable state. If small values of CT must be used, the pulse width may still be expanded by adding a shunt capacitance (= 100pF) to ground at the oscillator output. (Note: Although the oscillator output is a convenient oscilloscope sync input, the cable and input capacitance may increase the blanking pulse width slightly.) Obviously, the upper limit of the pulse width is determined by the maximum duty cycle acceptable. Practical values of CT fall between 0.01 and0.1 micro farad. The oscillator period is approximately t = RTCT where t is in microseconds when RT ohms and CT = micro farads. The selection of RT and CT can be made for a wide range of operating frequencies by using Fig. 7. Note that for sense regulator applications, the two outputs can be connected in parallel for an effective 090% duty cycle and the frequency of the oscillator is the frequency of the output. For push-pull applications, the outputs are separated and the flip-flop divides the frequency such that each output duty cycle is 0-45% and the overall frequency is onehalf that of the oscillator. External Synchronization If It is desired to synchronize the KA3524 to an external clock, a pulse of +3 volts may be applied to the oscillator output terminal with RTCT set slightly greater than the clock period. The same considerations of pulse width apply. The impedance to ground at this point is approximately 2K ohms. If two or more KA3524s must be synchronized together, one must be designated as the master with its RTCT set for the correct period. The slaves should each have an RTCT set for an approximately 10% longer period than the master with the added requirement that CT (slave) = one-half CT (master). Then connecting Pin 3 on all units together will insure that the master output pulse-which occurs first and has a wider pulse width - will reset the slave units. 4 KA3524 Error Amplifier This circuit is a simple differential-input, transconductance amplifier. The output is the compensation terminal pin 9, which is a high impedance node (RL:=5M). The gain is GV = gmRL = 8IL R L = 0.002 RL -------------2K T and can easily be reduced from a nominal of 10,000 by an external shunt resistance from pin 9 to ground, as shown in Figure 8,In addition to DC gain control, the compensation terminal is also the place for AC phase compensation. The frequency response curves of Figure 5 show the uncompensated amplifier with a single pole at approximately 200Hz and a unity gain cross-over frequency at 5MHz.typically, most output filter designs will introduce one or more addition poles at a significantly higher power frequency. Therefore, the best stabilizing network is a series R-C combination between pin 9 and ground which introduces a zero to cancel one of the output filter poles. A good starting point is 50K plus 0.001 micro farad. One final point on the compensation terminal is that this is also a convenient place to insert any programming signal which is to override the error amplifier. Internal shutdown and current limit circuits are connected here, but any other circuit which can sink 200uA can pull this point to ground, thus shutting off both outputs. While feedback is normally applied around the entire regulator, the error amplifier can be used with conventional operational amplifier feedback and is stable in either the inverting or noninverting mode. Regardless of the connections, however, input common-mode limits must be observed or output sign inversions may happen. For conventional regulator applications, the 5 volt reference voltage must be divided down as shown in Figure 3. The error amplifier may also be used in fixed duty cycle applications by using the unity gain configuration shown in the open loop test circuit. Current Limiting The current limiting circuitry of the KA3524 is shown in Figure 4. By matching the base-emitter voltages of Q1 and Q2, and assuming negligible voltage drop across R 1 : Threshold = VBE(Q1) + I 1R 2 - V BE(Q2) = l 1R 2 = 200mV Although this circuit provides a relatively small threshold with a negligible temperature coefficient, there are some limitations to its use, the most important of which is the 1 volt common mode range which requires sensing in the ground line. Another factor to consider is that the frequency compensation provided by R 1C1 and Q1 provides a roll-off pole at approximately 300Hz.Since the gain of this circuit is relatively low, there is a transition region as the current limit amplifier takes over pulse width control from the error amplifier. For testing purposes, the threshold is defined as the input voltage to get 25% duty cycle with the error amplifier signaling maximum duty cycle. In addition to constant current limiting, pins 4 and 5 may also be used in transformer-coupled circuits to sense primary current and shorten an output pulse, should transformer saturation occur. Another application is to ground pin 5 and use pin 4 as an additional shutdown terminal: i.e., the output will be off with pin 4 open and on when it is grounded. Finally, fold back current limiting can be provided with the network of Figure 5. This circuit can reduce the short circuit current (lSC)to approximately one third the maximum available output current (I MAX). Figure 3. Error Amplifier Biasing Circuits 5 KA3524 Figure 4. Current Limiting Circuit Of The KA3524 Figure 5. Foldback Current Limiting 6 KA3524 Typical Performance Characteristics Figure 6. Output Stage Dead Time As A Function Figure 7. Oscillator Period As A Function Of Rt And Ct Of The Timing Capacitor Value Figure 8. Amplifies Open-loop Gain As A Function Of Freguency And Loading On Pin 9 7 KA3524 Typical Applications Figure 9. Capacitor-diode Output Circuit Figure 10. Flyback Converter Circuit Figure 11. Single-ended Lc Circuit 8 KA3524 Figure 12. Push-pull Transformer-coupled Circuit 9 KA3524 Mechanical Dimensions Package Dimensions in millimeters 16-DIP ( #1 #16 0.81 ) 0.032 6.40 0.20 0.252 0.008 19.80 MAX 0.780 19.40 0.20 0.764 0.008 #8 #9 7.62 0.300 3.25 0.20 0.128 0.008 0.38 0.014 MIN 5.08 MAX 0.200 3.30 0.30 0.130 0.012 0~15 0.25 -0.05 0.010 -0.002 +0.004 +0.10 10 2.54 0.100 0.46 0.10 0.018 0.004 1.50 0.10 0.059 0.004 KA3524 Ordering Information Product Number KA3524 Package 16-DIP Operating Temperature 0 ~ 70C 11 KA3524 DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR INTERNATIONAL. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. www.fairchildsemi.com 9/25/00 0.0m 001 Stock#DSxxxxxxxx 2000 Fairchild Semiconductor International 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. |
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